Design signals across power and clock domains

Q: Design signals across power and clock domains

This is a System Design interview question from NVIDIA for Software Engineer roles. View the full question and solution on PracHub.

Q: How do I approach System Design interview questions?

System Design questions require understanding of core concepts and practice. PracHub provides solutions with explanations to help you master system design interviews.

Question

Interface Design for A → B Signal Across Power and Clock Domains

Context: You are designing an SoC with two power domains, A and B. A signal (signal_1) is generated in domain A and consumed in domain B. Domains may have different voltages, may power on/off independently, and may use different clocks.

Address the following:

Normal Operation (Power and Voltage): How would you architect signal_1 for A → B, including required cells (level shifters, isolation) and their placement (always-on vs. switchable)?
Different Clock Domains (CDC): If A and B use different clocks and signal_1 must meet timing/ordering requirements, what timing and CDC constraints would you add, and which design techniques (synchronizers, handshakes, FIFOs) would you use?
Same Clock Domain: How does the approach change if A and B share the same clock? What constraints remain, and how would you verify timing?
Feedthrough via B (A → B → A): If signal_1 passes A → B → A, how do you handle cases where B is powered off? Should isolation clamp to 1, 0, or another scheme (retention/latched), and how do you decide and verify using power intent (UPF/CPF) and signoff checks?

Design signals across power and clock domains

Interface Design for A → B Signal Across Power and Clock Domains

Solution

Comments (0)