You are writing RTL (e.g., Verilog/SystemVerilog) and run a lint tool on your code.
The tool reports items such as:
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"Treat as black box"
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Combinational loop
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Left-hand side (LHS) / right-hand side (RHS) not equal length (width mismatch)
Explain for each of these:
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What situation usually causes the warning or error.
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Why it can be dangerous if left unfixed.
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Typical ways you would investigate and fix the issue in your RTL.
Also briefly describe why running lint is important in a digital design flow.