This question evaluates a candidate's ability to design memory-aware control systems, covering skills such as hysteresis-based thresholding, dynamic runtime reconfiguration, thread-safe concurrency, low-overhead metric sampling, event-driven state notifications, and handling multi-process and failure edge cases.
You are designing an in-memory component ("Switcher") that gates expensive work (e.g., request admission, cache growth, background jobs) based on the process's runtime memory usage. The switcher exposes an ENABLED/DISABLED state with hysteresis to avoid flapping and supports live reconfiguration.
Assume the switcher runs within a single service process by default, but may be used in multi-process or multi-instance deployments.
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