##### Question In a SoC with two power domains A and B, design the interface for a control signal `signal_1` (a registered 1-bit control such as an enable/start/ready) that originates in domain A and is consumed in domain B. A and B may run at different supply voltages (DVFS-capable) and may be independently power-gated. Address the following: 1. **Normal operation (A → B).** How would you architect `signal_1` for the A → B crossing? Specify the required boundary cells (e.g., level shifters, isolation cells, always-on buffers), the reset strategy at source and sink, and where each cell is placed (always-on vs. switchable rail). 2. **Different clock domains.** If A and B use different clocks and `signal_1` must meet timing/ordering requirements (not be treated as purely asynchronous garbage), which CDC scheme would you use (two-flop synchronizer, pulse-to-toggle, request/ack handshake, or async FIFO) and why? What STA/CDC constraints would you add (e.g., asynchronous clock groups, false paths, `set_max_delay -datapath_only`, `min_pulse_width`, `ASYNC_REG`)? What pitfalls must be avoided? 3. **Same clock domain.** How does the approach change if A and B share the same clock? What constraints remain, what do you drop, and how would you verify timing? 4. **Feedthrough via B (A → B → A).** If `signal_1` passes through logic in B and returns to A, how do you close timing/CDC across both crossings? If B can be powered off, how do you clamp/isolate the signal (to 0, to 1, last value via retention, or high-Z) and why? Where do you place the isolation, what powers it, and how do you handle retention and the wake-up sequence? How do you verify all of this with power intent (UPF/CPF) and low-power signoff?

An NVIDIA software/hardware engineering onsite system-design question on architecting a control-signal interface that crosses both power and clock domains in a SoC. Covers level shifters and isolation cells with always-on vs. switchable placement, clock-domain-crossing schemes (two-flop synchronizers, pulse-to-toggle, request/ack handshakes, async FIFOs) and their STA/CDC constraints, the same-clock simplification, and the A→B→A feedthrough case with clamp choice, retention, wake-up sequencing, and UPF/CPF low-power signoff.

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Design signals across power and clock domains

Question

In a SoC with two power domains A and B, design the interface for a control signal signal_1 (a registered 1-bit control such as an enable/start/ready) that originates in domain A and is consumed in domain B. A and B may run at different supply voltages (DVFS-capable) and may be independently power-gated. Address the following:

Normal operation (A → B). How would you architect signal_1 for the A → B crossing? Specify the required boundary cells (e.g., level shifters, isolation cells, always-on buffers), the reset strategy at source and sink, and where each cell is placed (always-on vs. switchable rail).
Different clock domains. If A and B use different clocks and signal_1 must meet timing/ordering requirements (not be treated as purely asynchronous garbage), which CDC scheme would you use (two-flop synchronizer, pulse-to-toggle, request/ack handshake, or async FIFO) and why? What STA/CDC constraints would you add (e.g., asynchronous clock groups, false paths, set_max_delay -datapath_only , min_pulse_width , ASYNC_REG )? What pitfalls must be avoided?
Same clock domain. How does the approach change if A and B share the same clock? What constraints remain, what do you drop, and how would you verify timing?
Feedthrough via B (A → B → A). If signal_1 passes through logic in B and returns to A, how do you close timing/CDC across both crossings? If B can be powered off, how do you clamp/isolate the signal (to 0, to 1, last value via retention, or high-Z) and why? Where do you place the isolation, what powers it, and how do you handle retention and the wake-up sequence? How do you verify all of this with power intent (UPF/CPF) and low-power signoff?

Question

Normal operation (A → B). How would you architect signal_1 for the A → B crossing? Specify the required boundary cells (e.g., level shifters, isolation cells, always-on buffers), the reset strategy at source and sink, and where each cell is placed (always-on vs. switchable rail).
Different clock domains. If A and B use different clocks and signal_1 must meet timing/ordering requirements (not be treated as purely asynchronous garbage), which CDC scheme would you use (two-flop synchronizer, pulse-to-toggle, request/ack handshake, or async FIFO) and why? What STA/CDC constraints would you add (e.g., asynchronous clock groups, false paths, set_max_delay -datapath_only , min_pulse_width , ASYNC_REG )? What pitfalls must be avoided?
Same clock domain. How does the approach change if A and B share the same clock? What constraints remain, what do you drop, and how would you verify timing?
Feedthrough via B (A → B → A). If signal_1 passes through logic in B and returns to A, how do you close timing/CDC across both crossings? If B can be powered off, how do you clamp/isolate the signal (to 0, to 1, last value via retention, or high-Z) and why? Where do you place the isolation, what powers it, and how do you handle retention and the wake-up sequence? How do you verify all of this with power intent (UPF/CPF) and low-power signoff?

Design signals across power and clock domains

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Design signals across power and clock domains

Question

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Design signals across power and clock domains

Quick Overview

Design signals across power and clock domains

Question

Submit Your Answer to Earn 20XP