Design signals across power and clock domains

In a SoC with two power domains A and B, design the interface for a signal (signal_ 1) that originates in A and is consumed in B. Address the following: ( 1) Normal operation: how would you architect signal_1 for A->B, including required cells (e.g., level shifters, isolation) and their placement (always-on vs. switchable)? ( 2) Different clock domains: if A and B use different clocks and signal_1 must meet timing/ordering requirements, what timing and CDC constraints would you add, and which design techniques (e.g., synchronizers, handshakes, FIFOs) would you use? ( 3) Same clock domain: how does the approach change if A and B share the same clock; what constraints remain, and how would you verify timing? ( 4) Feedthrough via B: if signal_1 passes A -> B -> A, how do you handle cases where B is powered off; should isolation clamp to 1, 0, or another scheme (e.g., retention/latched), and how do you decide and verify using power intent (UPF/CPF) and signoff checks?