Given two power domains A and B in a SoC: 1) Under normal operation, how would you design a one-bit control signal S1 that travels from A to B? Specify required cells (e.g., level shifter, isolation, always-on buffers), reset strategy, and where each cell is placed. 2) If A and B are in different clock domains and S1 is timing-aware (not purely asynchronous), what CDC scheme would you use (e.g., two-flop synchronizer, request/ack handshake, or async FIFO), and what STA/CDC constraints would you add (e.g., multicycle, false-path, max_delay, min_pulse_width)? What pitfalls should be avoided? 3) If A and B share the same clock domain, how does your design and constraint set change versus the different-clock-domain case? 4) If the path is A → B → A (S1 feeds through logic in B), how do you close timing/CDC across both crossings? If B can power off, how do you clamp/iso S1 (to 0, to 1, last value, or high‑Z) and why? Where do you place the isolation, what powers it, and how do you handle retention and wake-up sequencing?

This question evaluates a candidate's understanding of SoC cross-power and clock-domain signal interfacing, including power-domain isolation, level shifting, reset and retention strategies, and clock-domain crossing and timing-constraint techniques.

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This is a hard difficulty System Design question, commonly asked during Onsite rounds at NVIDIA.

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This question is commonly asked for Software Engineer candidates at NVIDIA during technical interviews.

Design cross-power/clock-domain signal interface

Cross-Power/Clock-Domain Design for a 1‑bit Control S1 (A → B → A)

Context

You are designing a SoC with two power domains (voltage islands) A and B. A one‑bit control signal S1 originates in domain A and is consumed in domain B. A and B may have different voltages and may or may not share the same clock. Domain B can be power‑gated (off) while A remains on. Design the path(s) and constraints so the system is robust across normal operation, clock-domain crossings (CDC), and power‑gating.

Tasks

Normal operation design (A → B): Describe how you would implement S1 crossing from A to B. Specify:
- Which cells are required (level shifter, isolation, always‑on buffers, etc.).
- Reset strategy (assert/deassert style, per domain, synchronizers).
- Where each cell is placed and what powers it.
Different clock domains and S1 is timing‑aware (not purely asynchronous): Choose a CDC scheme (two‑flop synchronizer, request/ack handshake, toggle, or async FIFO) and list the STA/CDC constraints you would add (e.g., multicycle, false‑path, max_delay, min_pulse_width). Call out pitfalls to avoid.
Same clock domain: How does the design and constraint set change compared with the different‑clock‑domain case? What stays the same due to power/voltage concerns?
Round trip A → B → A (S1 feeds through logic in B): How do you close timing/CDC across both crossings? If B can power off, how do you clamp or isolate S1 (to 0, to 1, last value, or high‑Z) and why? Where do you place isolation, what powers it, and how do you handle retention and wake‑up sequencing?

Context

Tasks

Normal operation design (A → B): Describe how you would implement S1 crossing from A to B. Specify:

Which cells are required (level shifter, isolation, always‑on buffers, etc.).
Reset strategy (assert/deassert style, per domain, synchronizers).
Where each cell is placed and what powers it.

Different clock domains and S1 is timing‑aware (not purely asynchronous): Choose a CDC scheme (two‑flop synchronizer, request/ack handshake, toggle, or async FIFO) and list the STA/CDC constraints you would add (e.g., multicycle, false‑path, max_delay, min_pulse_width). Call out pitfalls to avoid.

Same clock domain: How does the design and constraint set change compared with the different‑clock‑domain case? What stays the same due to power/voltage concerns?

Round trip A → B → A (S1 feeds through logic in B): How do you close timing/CDC across both crossings? If B can power off, how do you clamp or isolate S1 (to 0, to 1, last value, or high‑Z) and why? Where do you place isolation, what powers it, and how do you handle retention and wake‑up sequencing?

Design cross-power/clock-domain signal interface

Quick Overview

Cross-Power/Clock-Domain Design for a 1‑bit Control S1 (A → B → A)

Context

Tasks

Solution

Comments (0)

Design cross-power/clock-domain signal interface

Quick Overview

Cross-Power/Clock-Domain Design for a 1‑bit Control S1 (A → B → A)

Context

Tasks

Solution

Comments (0)