Analyze an Instruction Trace with Latency, Throughput, Cache, and Roofline Constraints
Company: Imc
Role: Hardware Engineer
Category: Software Engineering Fundamentals
Difficulty: easy
Interview Round: Onsite
Overview: Analyze a simulated instruction trace using dependency latency, issue throughput, cache behavior, arithmetic intensity, and roofline bounds. The solution connects hardware evidence to algorithm, layout, blocking, batching, and vectorization changes while preserving correctness and exposing the next bottleneck.
Read the full Imc Hardware Engineer interview experience this question came from