Explain Cache Conflicts and Related Memory-Access Problems

Explain a cache-line conflict using an address-level example, then distinguish it from false sharing and GPU shared-memory bank conflicts. ### Constraints & Assumptions The source uses the term cache-line conflict without a hardware specification. First clarify the intended mechanism. For a concrete cache-set example, assume a set-associative cache with line size L bytes, S sets, and A ways, using set index `floor(address/L) mod S`. ### Clarifying Questions Is the concern cache-set eviction, coherence traffic between CPU cores, or scratchpad bank serialization on a GPU? What are the access pattern, alignment, and hardware mapping? ### What a Strong Answer Covers A concrete mapping from addresses to lines/sets, the resulting contention, and remedies appropriate to the actual mechanism. ### Follow-up Questions How can a working set smaller than total cache capacity still thrash? Why can padding help? When would padding merely increase memory use without addressing the bottleneck?