Explain Virtual Memory, MMUs, and TLBs

Walk through what happens when a process loads from a virtual address. Explain the roles of page tables, the memory-management unit, the translation lookaside buffer, page faults, protection bits, and context switches. ### Constraints & Assumptions - Separate address translation from cache lookup and physical memory access. - Distinguish a TLB miss from a page fault. - Acknowledge that exact page-table formats and cache ordering vary by architecture. ### Clarifying Questions to Ask - Which architecture and page size should be assumed? - Is the page resident, swapped out, or unmapped in the scenario? - Does the question include multi-core TLB shootdowns? ### What a Strong Answer Covers - Virtual-page and offset decomposition and a TLB lookup. - A hardware or assisted page-table walk on a TLB miss. - Permission checks and accessed or dirty state. - The operating-system path for valid nonresident pages versus invalid access. - Address-space identifiers, context switching, huge pages, shootdowns, and performance trade-offs. ### Follow-up Questions - Why can a program have many TLB misses without any page faults? - How do huge pages change TLB reach and fragmentation? - What must happen when one core changes a page-table entry used by other cores?