Row-Wise vs Column-Wise Array Reads, L1/L2 Caches, and the TLB
Company: Axq Capital
Role: Software Engineer
Category: Software Engineering Fundamentals
Difficulty: medium
Interview Round: HR Screen
Overview: Compare horizontal and vertical reads of a large two-dimensional array, explain how L1 and L2 caches differ from main memory, and describe what the TLB does and what a TLB miss costs. It tests understanding of cache lines, locality, prefetching, address translation, and practical fixes for memory-bound code.