Trace an LLM Request Through a Paged-KV Inference Engine

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Quick Overview

Trace LLM inference from request admission through prefill and decoding, explaining paged KV block tables, continuous batching, cache lifetime, and latency tradeoffs.

Trace an LLM Request Through a Paged-KV Inference Engine

Company: AMD

Role: Software Engineer

Category: ML System Design

Difficulty: medium

Interview Round: Onsite

Trace a prompt through an LLM inference engine, using a vLLM-style paged-KV architecture as the reference. Explain request admission, prefill, decoding, PagedAttention, the KV-cache block table, and continuous batching. ### Constraints & Assumptions Discuss the architecture and invariants rather than a particular library release or internal class name. State model, context-length, latency, and memory assumptions when they affect the design. ### Clarifying Questions How long are prompts and outputs? What does the latency target measure? Can prefixes be shared? What happens when KV-cache capacity is exhausted? Is the request streamed? ### What a Strong Answer Covers A coherent request lifecycle, logical-to-physical KV mapping, iteration-level scheduling, cache ownership, and the relation between throughput and latency. ### Follow-up Questions Why can contiguous per-request KV allocation waste memory? How do block tables enable noncontiguous storage? What changes when requests finish at different times or long prompts enter an active batch?

Overview: Trace LLM inference from request admission through prefill and decoding, explaining paged KV block tables, continuous batching, cache lifetime, and latency tradeoffs.

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Sep 14, 2026
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Trace a prompt through an LLM inference engine, using a vLLM-style paged-KV architecture as the reference. Explain request admission, prefill, decoding, PagedAttention, the KV-cache block table, and continuous batching.

Constraints & Assumptions

Discuss the architecture and invariants rather than a particular library release or internal class name. State model, context-length, latency, and memory assumptions when they affect the design.

Clarifying Questions Guidance

How long are prompts and outputs? What does the latency target measure? Can prefixes be shared? What happens when KV-cache capacity is exhausted? Is the request streamed?

What a Strong Answer Covers Guidance

A coherent request lifecycle, logical-to-physical KV mapping, iteration-level scheduling, cache ownership, and the relation between throughput and latency.

Follow-up Questions Guidance

Why can contiguous per-request KV allocation waste memory? How do block tables enable noncontiguous storage? What changes when requests finish at different times or long prompts enter an active batch?

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