Hi everyone! The job search grind is finally over, and I landed the offer I wanted. Along the way I read countless useful posts from people who came before me on this forum, and I learned a lot from them. Today I want to give back and summarize the interview experience and high-frequency topics that I and the friends around me ran into applying for ASIC Design Verification (DV) roles in North America and at North American sites. Hopefully this helps anyone still looking for an internship or full-time role!
1. Personal Background and Interview Overview
Background: ECE / CE Master's degree, completed 2 full UVM-based verification projects during school, plus one internship at a major chip company.
Interview record: Got phone screens and final round/onsite interviews from multiple companies including Apple, Qualcomm, Nvidia, Synopsys, and Rambus.
Impressions of each company's interview style:
Apple: Hardcore technical. They rotate through everything from low-level C/C++ and Computer Architecture to SV/UVM and scripting, rarely touch behavioral questions, and care a lot about deep understanding of fundamentals and clean, hand-written code.
Qualcomm / Nvidia: Very focused on digital circuit fundamentals, CDC handling, FIFO depth calculations, and deep dives into your projects. They ask a lot of hand-written Constraint and Assertion problems.
2. Core High-Frequency Topics Summary (Must-Know for DV Interviews)
In DV interviews, interviewers tend to dig deep into the following 7 modules — I'd suggest organizing your prep by topic:
1. SystemVerilog & OOP Fundamentals
- Blocking (=) vs Non-blocking (<=): Why do combinational logic use blocking assignments and sequential logic use non-blocking? What simulation issues arise if you mistakenly use non-blocking in combinational logic?
- always_comb vs always @(*): How does always_comb behave differently at time 0? (It automatically triggers one evaluation at time 0.)
- Interface & Clocking Block: Why use a virtual interface? (A class is a dynamic object and can't directly contain a static hardware interface — it has to reference one through a pointer-like virtual interface.) How does a clocking block solve race conditions in simulation?
- OOP's three core traits and $cast: What is the purpose of polymorphism? Why do base class functions need to be virtual? What's the difference between downcasting and upcasting with $cast? When a parent class pointer points to a child class object, how does $cast check type safety?
- Bit manipulation: How do you flip/clear a specific bit in one line of code? Count the number of 1s in a 32-bit variable (a bit-counting algorithm).
2. UVM Framework and Mechanisms
- UVM phase mechanism: What order do the phases execute in? (Build -> Connect -> End_of_elaboration -> Start_of_simulation -> Run -> Extract -> Check -> Report.) Which phases are top-down and which are bottom-up? Which phase consumes simulation time? (run_phase is the only one that's a task; all the others are functions.)
- Factory override: What's the difference between type override and instance override? In which phase does a factory override take effect? (The build phase.)
- TLM ports and handshaking: How do the sequencer and driver handshake through seq_item_port? (get_next_item / item_done.) How do the monitor and scoreboard communicate via broadcast through uvm_analysis_port?
- Component vs Object: What's the difference in lifecycle? (A component persists through the whole simulation; an object is created and destroyed as needed.)
3. Constraint (Randomization Constraints) — Commonly Hand-Written on the Spot
Interviews frequently ask you to hand-write SystemVerilog constraints on the spot:
- One-hot constraint (without $onehot):
(a & (a - 1)) == 0 && a != 0 - Any 5 consecutive elements must be distinct:
constraint unique_5_c {
foreach (arr[i]) {
if (i < arr.size() - 4) {
unique {arr[i], arr[i+1], arr[i+2], arr[i+3], arr[i+4]};
}
}
}
- Array elements must be increasing, with adjacent elements differing by at least 2.
4. CDC (Clock Domain Crossing) & Digital Circuit Fundamentals
- CDC solutions: Single bit — dual-flop synchronizer (2-stage synchronizer); how do you calculate MTBF? Multi-bit — handshake protocol or asynchronous FIFO.
- FIFO depth calculation: Given burst length, read/write clock frequency, and read/write latency/throughput, derive on the spot the minimum FIFO depth needed to avoid deadlock. (Very common!)
- Setup / Hold time: What are the formulas for setup/hold violations? Which one is harder to fix? (Hold time only depends on path delay and is usually fixed by adding buffers.)
- Clock divider circuit design: Hand-write the Verilog implementation for even dividers (Div2, Div4) and odd dividers (Div3, Div5 with 50% duty cycle).
5. Computer Architecture
- Cache mechanisms: Cache coherency protocols (MESI/MOESI state transition diagrams). The difference between inclusive and exclusive cache. Given cache size, line size, and number of ways, calculate the number of bits for index, tag, and offset by hand.
- Pipeline hazards: What causes structural, data, and control hazards, and how do you resolve them? (Bypassing/forwarding, stalling, register renaming.)
3. Recommended Prep Materials and Book List
Books:
- SystemVerilog for Verification (Spear & Tumbush): The classic SV verification bible, a must-read.
- Cracking Digital VLSI Verification Interview: A great problem set that covers most of the fundamental concept questions.
- UVM Practical Guide (Zhang Qiang): One of the clearest introductions to UVM.
Websites and papers:
- ChipVerify: the go-to resource for SV/UVM syntax and simple code examples.
- Cliff Cummings' SNUG papers: especially the classic papers on async FIFO design and CDC — interviewers love pulling questions directly from these.
4. Job Search Takeaways and Networking
Prioritize projects and coursework: make sure your resume has at least 2 complete UVM-based testbench projects. The keywords HR screens for most are UVM, SystemVerilog, and System Architecture.
Actively seek referrals: look for SDE/DV engineers on your target team through professional job-search groups and other professional communities — a referral that gets you in front of the hiring manager converts far better than a blind application through the company website.
Interview mindset: the market is very competitive right now. If you don't get an offer, don't doubt yourself — a lot of the time it just comes down to limited headcount, or the other side picking someone with more experience. During interviews, smile, talk through your thinking out loud, and show that you're a good team player — it goes a long way.
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