Answer OoO, caches, and memory-system questions
Company: Apple
Role: Software Engineer
Category: Software Engineering Fundamentals
Difficulty: medium
Interview Round: Technical Screen
You are interviewing for a CPU/DV role. Provide clear explanations (and small worked examples where useful) for the following computer architecture topics:
1) **Out-of-order (OoO) execution basics**: Describe the main structures in an OoO core (e.g., ROB, reservation stations/issue queue, load-store queue), and how an instruction flows through them.
2) **Branch prediction**:
- Explain how a **gshare** predictor works (indexing, global history register, counters).
- Given a branch outcome, describe how to update the pattern history table (2-bit counters) and the global history register.
3) **Register renaming / RAT tracing**: You are given a short instruction sequence with architectural registers. Explain how to update the rename map table (RAT) and what the final mapping is. (No need for a specific ISA; assume each destination register allocates a new physical register.)
4) **VLIW**: What is VLIW and how does it differ from superscalar OoO designs? Discuss compiler vs hardware complexity.
5) **Cache coherence**: What problem does coherence solve? Compare common protocols (e.g., MSI/MESI/MOESI) at a high level.
6) **Load/store subsystem questions**:
- What are the roles of a store buffer and a load-store queue?
- What does it mean for loads/stores to be speculative?
- For cache tags, when do you use virtual vs physical addresses?
7) **Copy-on-write (COW) after `fork()`**: In an OS using `fork()`, how can parent and child share physical pages initially, and how does the system detect a write that should trigger COW? What exception/fault occurs and what does the handler do?
8) **Cache indexing math**: Given cache capacity, block size, and associativity, show how to compute:
- number of sets
- index bits
- block offset bits
- tag bits (assuming a 32-bit address)
9) **VIPT caches and aliasing**: For a virtually indexed, physically tagged cache, explain why aliasing can occur and how designs avoid it (page coloring / size constraints / way prediction etc.).
10) **Async FIFO**: What problem does an asynchronous FIFO solve? Outline the standard gray-code pointer technique and why it’s needed.
Quick Answer: This question evaluates core computer-architecture and system-level skills—covering out-of-order execution structures, branch prediction (gshare) mechanics, register renaming/RAT tracing, VLIW versus superscalar tradeoffs, cache coherence protocols, load/store subsystem behavior, copy-on-write after fork, cache indexing math, VIPT aliasing, and asynchronous FIFO design—and is categorized under Software Engineering Fundamentals. It is commonly asked because it probes a candidate’s microarchitectural and OS understanding, performance reasoning, and ability to explain low-level (microarchitecture and system-level) concepts and interactions without requiring full ISA-specific implementations.