Explain SystemVerilog verification concepts and write constraints
Company: Apple
Role: Software Engineer
Category: Software Engineering Fundamentals
Difficulty: medium
Interview Round: Technical Screen
Answer the following SystemVerilog / DV questions. Use short explanations and, where appropriate, show small SV code snippets.
1) **Concurrency**: Explain the difference between `fork...join`, `fork...join_any`, and `fork...join_none`. When would you use each?
2) **Random constraints (non-overlapping regions)**: You need to randomize **5 memory regions**. Each region has a `start` address and a `size` (or `end`). Requirements:
- All regions must be within a given address range (e.g., `[BASE, LIMIT]`).
- No two regions may overlap.
- (Optional) Regions must be aligned to N bytes.
Describe how you would model this with constraints.
3) **Testbench architecture**: What are the typical components of a modern SV/UVM testbench? Briefly describe the role of each.
4) **Basic constraint syntax**:
- Constrain a random variable to be within upper/lower bounds.
- Use **weighted distribution** to make certain values or ranges more likely.
5) **OOP in SV**:
- Explain class inheritance, polymorphism, and the purpose of `virtual` functions.
6) **Assertions for a small design**: You implemented an **edge detector** (detect rising edges of an input). Write example assertions to verify that:
- `edge` only pulses for one cycle on a rising transition.
- `edge` does not assert when the input is stable.
7) **Constraint ordering / dependency**:
- In randomization, what does `solve A before B` do?
- Give an example where adding/removing `solve before` changes the resulting distribution.
8) **Synchronization primitives**:
- Explain what a `semaphore` is and when you’d use it.
- Explain what a `mailbox` is and when you’d use it.
9) **Uniqueness and controlled repetition via constraints**:
- Constrain an array to produce **10 unique random integers** within a range.
- Constrain 10 integers where **exactly 3 distinct values each appear twice**, and the remaining 4 values appear once.
10) **Randomized card draw**:
- Model drawing cards from a standard 52-card deck (rank + suit).
- Each draw must be **non-repeating** (sampling without replacement).
- The draw should be **uniform** over remaining cards (no bias). Describe an SV-friendly approach.
Quick Answer: This question evaluates proficiency with SystemVerilog verification concepts — including concurrency primitives, constrained-random modeling, assertions, OOP features, synchronization primitives, and testbench architecture — and tests the ability to specify non-overlapping/randomized constraints and reason about solve-order and sampling semantics; it is commonly asked because interviewers seek assurance that a candidate can build correct constrained-random testbenches and diagnose simulation or coverage issues. Category/domain: Software Engineering Fundamentals with a focus on hardware design verification; level of abstraction: language-level implementation details and testbench architecture/behavioral verification concerns.