Assume you are designing a digital system with multiple clock domains. The clocks have different frequencies and unknown phase relationships. You can choose among several clock-domain crossing (CDC) techniques: - 2-stage flip-flop synchronizer (for a single bit) - Edge-detect synchronizer - Asynchronous FIFO - Request/acknowledge handshake Explain: 1. What problem clock synchronizers are solving (e.g., metastability, missing pulses). 2. When you would choose each of the above techniques. 3. The main trade-offs of each option in terms of reliability, latency, throughput, and area. Give concrete examples, such as crossing a single control signal vs. transferring a multi-bit data bus between domains with different average data rates.